High-voltage transistor with buried conduction layer

ABSTRACT

A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type source diffusion region, which connects to the source electrode, defines the other end of the gate region.

RELATED APPLICATION

[0001] This application is related to U.S. patent application Ser. No.09/245,029, filed Feb. 5, 1999, of Rumennik et al., which application isassigned to the assignee of the present application and is hereinincorporated by reference.

FIELD OF THE INVENTION

[0002] The present invention relates to semiconductor devices. Morespecifically, the present invention relates to high voltage field-effecttransistor structures fabricated in silicon substrates.

BACKGROUND OF THE INVENTION

[0003] Lateral, high-voltage, field-effect transistors (HVFETs) havebeen fabricated using an insulated gate field-effect transistor (IGFET)placed in series with a high-voltage junction field-effect transistor(JFET). The IGFET is used to control the “on” state current in thedevice and the JFET is used to support high-voltage in the “off” state.This HVFET structure can be switched at high voltages, has a lowon-state resistance, and has insulated-gate control. In addition, it mayadvantageously be fabricated near low voltage logic transistors on asingle integrated circuit chip.

[0004] Lateral HVFETs are commonly fabricated in accordance with theReduced Surface Field (RESURF) principle. The RESURF principle, however,mandates that the charge in the extended drain region, which serves asthe channel of a lateral JFET, be carefully controlled to obtain highbreakdown voltage. To keep the maximum electric field below the criticalfield at which avalanche breakdown occurs the amount of charge in theJFET channel is typically limited to a maximum of about 1×10¹² cm⁻².When the HVFET is in the “on” state, the resistance of the JFET channelconstitutes a large portion of the on-state resistance of the HVFET.Therefore, the limitation on the maximum charge in the JFET channel alsosets the minimum specific on-resistance of the device.

[0005] A HVFET having an extended drain region with a top layer of aconductivity type opposite that of the extended drain region isdisclosed in U.S. Pat. No. 4,811,075. The '075 patent teaches that thetop layer nearly doubles the charge in the conducting layer, with acommensurate reduction in device on-resistance. This top layer alsohelps to deplete the JFET conduction region when the extended drain issupporting a high voltage.

[0006] Further extending this concept, U.S. Pat. No. 5,411,901 teachesutilizing the opposite conductivity type top layer as the conductingportion of the JFET in a complementary high-voltage transistor. Onedrawback, however, is that construction of this complementary devicerequires additional processing steps to achieve high-voltage capability.Additionally, the on-resistance of the complementary device is limitedby the charge requirement for the top region (e.g., about 1×10¹² cm⁻²).Another difficulty is that the top layer is often formed prior tooxidation of the silicon surface, which introduces additional processvariation.

[0007] To further increase the total charge in the conducting region ofthe JFET and reduce on-resistance, U.S. Pat. No. 5,313,082 teaches aHVFET structure in which two JFET channels are arranged in parallel. Atriple diffusion process is disclosed, in which three separate implantand diffusion steps are required to form a HVFET having an N-typeconducting top layer, a P-type middle layer, and an N-type conductingbottom layer. The multiple layers of alternating conductivity types arefabricated by implanting, and then diffusing, dopants into thesemiconductor substrate. The '082 patent also describes a complementaryhigh-voltage transistor (i.e., a P-channel device) that is formed byadding an additional layer to the three-layer extended drift region.

[0008] One shortcoming of this prior art approach is that eachsuccessive layer is required to have a surface concentration that ishigher than the preceding layer, in order to fully compensate and changethe conductivity type of the corresponding region. Diffusion of dopantsfrom the surface makes it very difficult to maintain adequate chargebalance among the layers. In addition, the heavily doped P-N junctionbetween the buried layer and drain diffusion region degrades thebreakdown voltage of the device. The concentrations also tend to degradethe mobility of free carriers in each layer, thereby compromising theon-resistance of the HVFET. The additional layer required for making thecomplementary device also complicates the manufacturing process.

[0009] A p-channel MOS device design that is compatible with a genericprocess for manufacturing complementary CMOS devices is disclosed inU.S. Pat. No. 5,894,154.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present invention is illustrated by way of example, and notlimitation, in the figures of the accompanying drawings, wherein:

[0011]FIG. 1 is a cross-sectional side view of one embodiment of ahigh-voltage, field-effect transistor (HVFET) device structure inaccordance with the present invention.

[0012]FIG. 2 is a cross-sectional side view of another embodiment of aHVFET fabricated in accordance with the present invention.

[0013]FIG. 3 is a cross-sectional side view of complementary HVFETsfabricated on the same substrate in accordance with the presentinvention.

DETAILED DESCRIPTION

[0014] A high-voltage field-effect transistor is described. The HVFEThas a low specific on-state resistance, and can be easily integratedwith a complementary lateral HVFET on the same chip along with lowvoltage logic devices. In the following description, numerous specificdetails are set forth, such as material types, doping levels, structuralfeatures, processing steps, etc., in order to provide a thoroughunderstanding of the present invention. Practitioners having ordinaryskill in the semiconductor arts will understand that the invention maybe practiced without many of these details. In other instances,well-known elements, techniques, and processing steps have not beendescribed in detail to avoid obscuring the invention.

[0015]FIG. 1 is a cross-sectional side view of a p-channel HVFET devicestructure in accordance with one embodiment of the present invention.(It should also be understood that the elements in the figures arerepresentational, and are not drawn to scale in the interest ofclarity.) An N-channel transistor may be realized by utilizing theopposite conductivity types for all of the illustrated diffusionregions. The device of FIG. 1 includes an insulated-gate, field-effecttransistor (IGFET) having a gate 22 (comprised, for example, ofpolysilicon), an gate insulating layer 30, comprised of silicon dioxideor another appropriate dielectric insulating material, and an underlyingN-type well region 12 disposed in a lightly-doped P-type substrateregion 10. The area of n-type well region 12 directly beneath gate 22comprises the IGFET channel region 31 of the transistor. In thisembodiment, the gate region is a metal-oxide semiconductor (MOS), andthe IGFET is a PMOS transistor.

[0016] Channel region 31 is defined at one end by P+ source diffusionregion 19 and at the other end by P-type diffusion region 16, whichextends down from the substrate surface of N-well 12. A lateralhigh-voltage p-channel FET is formed by the series connection of thePMOS device and a P-type JFET transistor formed by high-energyimplantation of a P-type dopant (e.g., boron) into N-well region 12.This high-energy implantation forms P-type buried layer 14, which isconnected to and p-type diffusion region 16. Buried layer 14 comprisesthe conducting portion of the extended drain of the P-type JFET device.The charge in P-type buried region 14 is approximately 2×10¹² cm⁻² inthis embodiment, resulting in an on-resistance that is about 50% lowerthat traditional devices.

[0017] Practitioners in the art will appreciate that the doping inP-type diffusion region 16 is chosen so that this region can be fullydepleted at a relatively low voltage (<100V) in the off state. Thisinsures that region 16 does not interfere with the ability of thetransistor to support high voltage (˜700V) in the off state.

[0018] A source electrode 29 provides an electrical connection to P+source diffusion region 19. Similarly, a drain electrode 28 connects toa P+ drain diffusion region 18. Drain diffusion region 18 and sourcediffusion region 19 may be formed using the same implant steps.Electrical connection between drain diffusion region 18 and buried layer14 is established via P-type diffusion region 17. It is understood thatregion 17 may be formed simultaneous with P-type diffusion region 16using the same processing steps. Alternatively, P+ drain diffusionregion 18 may be formed to extend vertically from the substrate surfacedown to P-type buried layer 14.

[0019] Respective source and drain electrodes 29 and 28 may comprise anumber of widely used metals or metal alloys. Note that source electrode29 is shown extending over, and insulated from, gate 22 where itfunctions as a field plate. Similarly, drain electrode 28 extends overpolysilicon field plate member 23, disposed above and adjacent to draindiffusion region 18. Field plating acts to reduce the surface electricfield and increase the effective radius for depletion of the substrate,thereby increasing the breakdown voltage of the transistor.

[0020] In the embodiment of FIG. 1, a N+ diffusion region 20 is disposedadjacent to P+ source diffusion region 19. Diffusion region 20 providesgood electrical connection to N-well region 12 and thus reducessusceptibility of the device to parasitic bipolar effects.

[0021] When the P-channel HVFET of FIG. 1 is in the on-state, currentflows from the source diffusion region 19 through the IGFET channelregion 31 and then through P-type regions 16, 14, and 17 to P+ draindiffusion region 18. As discussed above, the charge in P-type buriedregion 14 is approximately twice as high than that of a conventionalP-channel device. Thus, the resistance of the extended drain region isreduced to about ½ that of a conventional device.

[0022] In the off state, P-diffusion region 16, P-type buried layerregion 14, and N-well region 12 are mutually depleted of free carriers.

[0023] An important advantage of the device structure shown in FIG. 1 isthat it can be constructed using the same process used to fabricate acomplementary, high-voltage, N-channel FET. For instance, such a processis set forth in FIGS. 11a-11 i and the associated description of theincorporated Rumennik et al. patent application. Significantly, noadditional processing complexity is introduced since the same maskinglayers may be used for both devices, other than the addition of P-typeregion 16.

[0024] In accordance with the aforementioned process for fabricating anN-channel HVFET, building a complementary device on the same siliconsubstrate can be accomplished by segregating the respective N-wellregions associated with the P-channel and N-channel devices. Themasking-layer used to form P-type buried layer region 14 of theP-channel device can be used to simultaneously form the buried layerregion of the N-channel device structure. In the N-channel device, thisP-type buried layer divides the single conductive N-well into parallelconductive drift regions of the JFET transistor. Added in parallel, eachconductive region reduces the on-resistance of the HVFET structure.

[0025] By way of example, FIG. 3 illustrates high-voltage PMOS and NMOStransistors fabricated adjacent to one another on the same P-typesubstrate 10. Note that the same processing steps used to form N-well 12of the PMOS device may also be used to fabricate N-Well 52 of the NMOSdevice. Similarly, buried layer 14 of the PMOS device and buried layer74 of the NMOS device may be formed using the same steps. Other regionsof the PMOS and NMOS devices that can be formed with the same processingsteps include P+ regions 19 and 69, N+ regions 20 and 70, and gate oxideregions 30 and 80, respectively.

[0026] P-type diffusion region 16 of FIG. 1, for example, may be formedeither before or after the implantation step that forms the P-typeburied layer regions of the N-channel and P-channel devices. By way ofexample, diffusion region 16 may be formed by implantation of boron intothe substrate following formation of N-well 12. If the processoptionally includes steps for forming a field oxide layer, P-typediffusion region 16 may be formed in N-well 12 either prior to fieldoxide growth, or afterward, utilizing conventional processingtechniques.

[0027]FIG. 2 illustrates an alternative embodiment of the presentinvention, which comprises a plurality of vertically stacked P-typeburied layer regions 14 a-14 c disposed in N-well region 12. In atypical processing sequence, a single implant mask is used to define allof the buried layers. High-energy implantation is then used to formburied layer region 14 a, 14 b, and 14 c. The device structure of FIG. 2includes a P-type diffusion region 26, which defines one end of channel31. Diffusion region 26 extends down from the substrate surface toelectrically connect with each of buried layer regions 14 a-14 c.Similarly, P-type diffusion region 27 extends vertically down from P+drain diffusion region 18 to connect with each of buried layer regions14 a-14 c. Instead of forming a separate P-type region 27, theconnection to each of buried layer regions 14 beneath drain diffusionregion 18 may be achieved by simply extending P+ drain diffusion region18 vertically down from the substrate surface to a depth sufficient toconnect with buried layer regions 14 a-14 c.

[0028] Thus, the spaced-apart P-type buried layer regions 14 in theHVFET of FIG. 2 provide parallel conduction paths. By controlling thecharge in each of the buried layer regions 14 the ability of theP-channel device to support high voltage in not compromised. Moreover,in accordance with the above teachings, each additional conducting layercontributes an additional 2×10¹² cm⁻² of charge to further lower theon-resistance of the device.

I claim:
 1. A high-voltage field-effect transistor (HVFET) comprising: a substrate of a first conductivity type; a well region of a second conductivity type, opposite to the first conductivity type, disposed in the substrate; a source diffusion region of the first conductivity type disposed in the N-well region; a first drain diffusion region of the first conductivity type disposed in the N-well region spaced-apart from the source diffusion region, a channel region being defined in the well region between the source diffusion region and the first drain diffusion region; a second drain diffusion region of the first conductivity type disposed in the well region spaced-apart from the first drain diffusion region; a buried layer region of the first conductivity type disposed within the well region, extending laterally from beneath the first drain diffusion region to beneath the second drain diffusion region, the buried layer region being connected to both the first and second P-type drain diffusion regions such that current flows laterally through the buried layer region when the HVFET is in an on-state; and an insulated gate formed over the channel region.
 2. The HVFET according to claim 1 further comprising: a source electrode connected to the source diffusion region; and a drain electrode connected to the second drain diffusion region.
 3. The HVFET according to claim 2 further comprising: a diffusion region of the second conductivity type disposed in the well region adjacent the source diffusion region, the diffusion region being connected to the source electrode.
 4. The HVFET according to claim 2 wherein the first conductivity type is P-type and the second conductivity type is N-type, and the second drain diffusion region comprises: a P+ diffusion region connected to the drain electrode; and an additional P-type diffusion region that extends from the P+ diffusion region to the buried layer region.
 5. The HVFET according to claim 2 wherein the source and drain electrodes each comprise laterally extended portions that function as field plates.
 6. The HVFET according to claim 5 further comprising a drain field plate member disposed adjacent to and insulated from the second drain diffusion region, the drain field plate member also being disposed beneath and insulated from the laterally extended portion of the drain electrode.
 7. The HVFET according to claim 1 wherein the buried layer region comprises a plurality of buried layers.
 8. The HVFET according to claim 7 wherein the first drain diffusion region extends vertically in the well region to connect to each of the plurality of buried layers.
 9. The HVFET according to claim 8 wherein the second drain diffusion region extends vertically in the well region to connect to each of the plurality of buried layers.
 10. The HVFET according to claim 1 wherein the first drain diffusion region has a first surface that adjoins a surface of the substrate.
 11. The HVFET according to claim 1 wherein the first conductivity type is N-type and the second conductivity type is P-type.
 12. The HVFET according to claim 1 wherein the first drain diffusion region is depleted at a relatively low voltage.
 13. A high-voltage field-effect transistor (HVFET) comprising: a substrate of a first conductivity type; a well region of a second conductivity type opposite to the first conductivity type, the well region being disposed in the substrate; a source diffusion region of the first conductivity type disposed in the well region; a first drain diffusion region of the first conductivity type disposed in the well region laterally spaced-apart from the source diffusion region; a second drain diffusion region of the first conductivity type disposed in the well between the first drain diffusion region and the source diffusion region, a channel region being defined in the well region between the source diffusion region and the second drain diffusion region; a plurality of parallel, spaced-apart buried layers of the first conductivity type disposed within the well region, the buried layers extending laterally from beneath the first drain diffusion region to beneath the second drain diffusion region, the first and second drain diffusion regions extending vertically in the well region to connect to each of the buried layers such that current flows laterally through each of the buried layers when the HVFET is in an on-state; and an insulated gate formed over the channel region.
 14. The HVFET according to claim 13 further comprising: a source electrode connected to the source diffusion region; and a drain electrode connected to the first drain diffusion region.
 15. The HVFET according to claim 14 further comprising: a diffusion region of the second conductivity type disposed in the well region adjacent the source diffusion region, the diffusion region being connected to the source electrode.
 16. The HVFET according to claim 14 the first conductivity type is P-type and the second conductivity type is N-type, and the first drain diffusion region comprises: a P+ diffusion region connected to the drain electrode; and an additional P-type diffusion region that vertically extends down from the P+ diffusion region to each of the buried layers.
 17. The HVFET according to claim 14 wherein the source and drain electrodes each comprise laterally extended portions that function as field plates.
 18. The HVFET according to claim 17 further comprising a drain field plate member disposed adjacent to and insulated from the first drain diffusion region, the drain field plate member also being disposed beneath and insulated from the laterally extended portion of the drain electrode.
 19. The HVFET according to claim 13 wherein each of the buried layers are fully depleted at a relatively low voltage when the HVFET is in an off-state.
 20. The HVFET according to claim 14 wherein the first drain diffusion region comprises a diffusion region that contacts the drain electrode and extends vertically down in the well region to connect with each of the of buried layers.
 21. The HVFET according to claim 13 wherein the second drain diffusion region has a first surface that adjoins a surface of the substrate.
 22. The HVFET according to claim 13 wherein the first conductivity type is N-type and the second conductivity type is P-type.
 23. A method of fabricating a high-voltage field-effect transistor (HVFET) in a substrate of a first conductivity type comprising: forming a well of a second conductivity type opposite to the first conductivity type in the substrate; implanting a dopant of the first conductivity type into the well to form a laterally extended buried layer region of the first conductivity type within the well; forming an insulated gate above the well; forming a first drain region of the first conductivity type and a source region of the first conductivity type spaced-apart in the well region; forming a second drain region of the first conductivity type spaced-apart from the first drain region and located between the first drain region and the source region, a channel region being defined in the well between the source region and the second drain region under the insulated gate; and wherein the first and second drain regions extend vertically down through the well to connect with the buried layer region so that the buried layer region provides a conductivity path for current to flow laterally when the HVFET is in an on-state.
 24. The method according to claim 23 wherein the first conductivity type is P-type and the dopant comprises boron.
 25. The method according to claim 23 wherein the buried layer region comprises a plurality of parallel, spaced-apart buried layers disposed at different depths within the well.
 26. The method according to claim 23 wherein implanting the dopant to form the buried layer region within the well also forms another buried layer region of the first conductivity type for a complementary HVFET also disposed in the substrate.
 27. The method according to claim 23 further comprising: forming a source electrode connected to the first drain region; and forming a drain electrode connected to the source region.
 28. The method according to claim 24 wherein the first conductivity type is P-type and the second conductivity type is N-type, and forming the first drain region further comprises: forming a P+ region connected to the drain electrode; and forming an additional P-type region that extends from the P+ region down to the buried layer region.
 29. A method of fabricating complementary high-voltage field-effect transistors (HVFETs) in a substrate of a first conductivity type comprising: forming first and second well regions of a second conductivity type opposite to the first conductivity type in the substrate; implanting a dopant of the first conductivity type into the first and second well regions to form first and second laterally extended buried layer regions within the first and second well regions, respectively; forming a first insulated gate above the first well region, and a second insulated gate above the substrate adjacent the second well region; forming a first drain region and a first source region of the first conductivity type spaced-apart in the first well region, the first drain and source regions being associated with a first HVFET; forming an additional drain region of the first conductivity type in the first well region spaced-apart from the first drain region and located between the first drain region and the first source region, a first channel region being defined in the first well region between the first source region and the additional drain region under the first insulated gate; forming a second drain region of the second conductivity type in the second well region, and a second source region of the second conductivity type spaced-apart from the second well region, the second drain and source regions being associated with a second HVFET, a second channel region being defined between the second source region and the second well region under the second insulated gate; wherein the first and additional drain regions extend vertically down through the first well region to connect with the first laterally extended buried layer region so that the first laterally extended buried layer region provides a conductivity path for current to flow laterally when the first HVFET is in an on-state, the second laterally extended buried layer region defining corresponding JFET conduction paths in the second well when the second HVFET is in an on-state.
 30. The method according to claim 29 wherein the first conductivity type is P-type and the dopant comprises boron.
 31. The method according to claim 29 wherein the first and second laterally extended buried layer regions each comprise a plurality of parallel, spaced-apart buried layers disposed at different depths within the first and second well regions.
 32. The method according to claim 29 wherein the first and second laterally extended buried layer regions are formed simultaneously by implantation. 